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@documentencoding UTF-8

@ifnottex
@paragraphindent 0
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@titlepage
@title ThinkPad R500
@end titlepage

@node Top
@top ThinkPad R500

@menu
* ThinkPad R500::
* LCD compatibly::
* Issues::
* Descriptor differences::
* No Gbe region!::
@end menu

@node ThinkPad R500
@chapter ThinkPad R500
@anchor{#thinkpad-r500}
It is believed that all or most R500 laptops are compatible. See notes about @uref{../install/r500_external.html#cpu_compatibility,CPU compatibility} for potential incompatibilities.

There are two possible flash chip sizes for the R500: 4MiB (32Mbit) or 8MiB (64Mbit). This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. @strong{NOTE: this paragraph is being treated with contempt. When an R500 was disassembled, it didn't look like there was an extra place for SOIC-16. It's highly likely that these laptops only have SOIC-8 (4MiB) flash chips. For now, libreboot will distribute 8MiB images just in case. If it is found later on that no 8MiB (SOIC-16) chips exist on the R500, then libreboot will cease to distribute 8MiB ROM images for this laptop. It is only said that the R500 has 4MiB or 8MiB, for now, since this is the case on other GM45 thinkpads that are supported in libreboot.}

@strong{The R400 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it by using a modified descriptor: see @uref{gm45_remove_me.html,gm45_remove_me.html}} (contains notes, plus instructions)

Flashing instructions can be found at @uref{../install/index.html#flashrom,../install/index.html#flashrom}

@strong{NOTE: This board is unsupported in libreboot 20150518. To use it in libreboot, for now, you must build for it from source using the libreboot git repository.}

@uref{index.html,Back to previous index}.
@menu
* Compatibility without blobs::
@end menu

@node Compatibility without blobs
@section Compatibility (without blobs)
@anchor{#compatibility-without-blobs}
@menu
* Hardware virtualization vt-x::
@end menu

@node Hardware virtualization vt-x
@subsection Hardware virtualization (vt-x)
@anchor{#hardware-virtualization-vt-x}
The R400, when run without CPU microcode updates in coreboot, currently kernel panics if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled for the guest, the guest panics (but the host is fine). Working around this in QEMU might be possible; if not, software virtualization should work fine (it's just slower).

On GM45 hardware (with libreboot), make sure that the @emph{kvm} and @emph{kvm_intel} kernel modules are not loaded, when using QEMU.

The following errata datasheet from Intel might help with investigation: @uref{http://download.intel.com/design/mobile/specupdt/320121.pdf,http://download.intel.com/design/mobile/specupdt/320121.pdf}

@node LCD compatibly
@chapter LCD compatibly
@anchor{#lcd-compatibly}
Not all LCD panels are known to be compatible yet. See @uref{gm45_lcd.html,gm45_lcd.html}.

The R500 is almost identical to the X200, code-wise, but there are some hardware differences. See @uref{x200.html,x200.html}.
@menu
* Hardware register dumps::
@end menu

@node Hardware register dumps
@section Hardware register dumps
@anchor{#hardware-register-dumps}
The coreboot wiki @uref{http://www.coreboot.org/Motherboard_Porting_Guide,shows} how to collect various logs useful in porting to new boards. Following are outputs from the R500:

@itemize
@item
Lenovo BIOS 3.13 (EC firmware 1.06):
@itemize
@item
@url{../resources/misc/dumps/r500/}
@end itemize

@end itemize

@node Issues
@chapter Issues
@anchor{#issues}
@menu
* False report of overheating automatic shut down::
* Cardbus slot didn't work when tested::
@end menu

@node False report of overheating automatic shut down
@section False report of overheating, automatic shut down
@anchor{#false-report-of-overheating-automatic-shut-down}
When attempting to boot Trisquel 7 live USB (GNOME), the following error appears and then the system abruptly shuts down: @strong{thermal thermal_zone1: critical temperature reached(120 C),shutting down}.

This is false. When booting with @strong{acpi=off}, xsensors shows no overheating during a stress test. The system does not feel hot, nor does anything smell like it's burning.

This is most likely caused by an ACPI bug in coreboot, which will have to be investigated. Grep for those things, comparing factory/libreboot (iasl -d or acpidump):

@verbatim
 Return (C2K(\_SB.PCI0.LPCB.EC.TMP0))
TMP0, 8,        /* Thermal Zone 0 temperature */
@end verbatim

@node Cardbus slot didn't work when tested
@section Cardbus slot didn't work when tested
@anchor{#cardbus-slot-didnt-work-when-tested}
Investigate.

@node Descriptor differences
@chapter Descriptor differences
@anchor{#descriptor-differences}
The @emph{ich9gen} and @emph{ich9deblob} utilities were modified, to reflect these differences.
@menu
* Component 1 Density::
* flReg1LIMIT::
* Onboard gigabit ethernet NIC is disabled::
@end menu

@node Component 1 Density
@section Component 1 Density
@anchor{#component-1-density}

@verbatim
-    descriptorStruct.componentSection.flcomp.component1Density = 0x4;
+    descriptorStruct.componentSection.flcomp.component1Density = 0x3;
@end verbatim

Read page 848 in the ICH9 datasheet, linked to from @uref{gm45_remove_me.html#flash_descriptor_region,gm45_remove_me.html#flash_descriptor_region}. This doesn't break anything, but in the process of debugging descriptor differences on the R500, it was found that this config option isn't being modified in libreboot, for different size ROM images. 4MiB ROM images still contain 0x4 for component1Density. Per datasheets, 0x4 (100) is 8MiB, and 0x3 (011) is 4MiB. @strong{This should be fixed!}

It was 0x3 for this test, because the R500 that was used to create this report had a 4MiB SOIC-8 flash chip.

@node flReg1LIMIT
@section flReg1.LIMIT
@anchor{#flreg1.limit}

@verbatim
-    /* descriptorStruct.regionSection.flReg1.LIMIT = 0x07ff; */
+    /* descriptorStruct.regionSection.flReg1.LIMIT = 0x03ff; */
@end verbatim

Ignore this. This is not used at all, and is instead automatically set, depending on the targetted ROM image size, both in ich9gen and ich9deblob. 0x7ff means 8MiB, and 0x3ff means 4MiB. flReg1 is for the BIOS region. Simply speaking, this is defining the final 4KiB section of the ROM image, where the BIOS region ends.

It was 0x3ff for this test, because the R500 that was used to create this report had a 4MiB SOIC-8 flash chip.

@node Onboard gigabit ethernet NIC is disabled
@section Onboard gigabit ethernet NIC is disabled
@anchor{#onboard-gigabit-ethernet-nic-is-disabled}

@verbatim
-    descriptorStruct.ichStraps.ichStrap0.integratedGbe = 0x1;
-    descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x1;
+    descriptorStruct.ichStraps.ichStrap0.integratedGbe = 0x0;
+    descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x0;
@end verbatim

Most GM45 laptops (e.g. X200, T400, T500, R400) have the @strong{Intel 82567LM} integrated gigabit NIC.

On the R500, a @strong{Broadcom BCM5787M} NIC is present. To make this work, the change above must be made for the R500 descriptor.

@node No Gbe region!
@chapter No Gbe region!
@anchor{#no-gbe-region}
Not shown in the diffs above:

@verbatim
Original: Descriptor start block: 00000000 ; Descriptor end block: 00000000
Original: BIOS start block: 00200000 ; BIOS end block: 003ff000
Original: ME start block: 00001000 ; ME end block: 001f7000
Original: GBe start block: 00fff000 ; GBe end block: 00000000
Original: Platform start block: 001f8000 ; Platform end block: 001ff000
@end verbatim

As explained above, this laptop uses a Broadcom NIC, which means that the Gbe region does not and @emph{should not} exist, since this is for the Intel NIC only.

In the output above, Gbe starts at fff and ends at 000. Base 1FFF or FFF, and limit 0, means that the region is disabled.

In the output above, the ME region is 4KiB larger than on other GM45 systems that have a Gbe region. This accounts for the lack of a Gbe region.

As part of this effort, ich9gen/ich9deblob/demefactory will all be modified to account for the differences above.

Copyright © 2015 Francis Rowe <info@@gluglug.org.uk>@* Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license can be found at @uref{../resources/licenses/gfdl-1.3.txt,gfdl-1.3.txt}

Updated versions of the license (when available) can be found at @uref{https://www.gnu.org/licenses/licenses.html,https://www.gnu.org/licenses/licenses.html}

UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU.

TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU.

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@bye
